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ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
DOUBLE DATA RATE (DDR) SDRAM
FEATURES
* VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data www..com capture (x16 has two - one per byte) * Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four internal banks for concurrent operation * Data mask (DM) for masking write data (x16 has two - one per byte) * Programmable burst lengths: 2, 4, or 8 * x16 has programmable IOL/IOV. * Concurrent auto precharge option is supported * Auto Refresh and Self Refresh Modes * Longer lead TSOP for improved reliability (OCPL) * 2.5V I/O (SSTL_2 compatible)
MT46V128M4 - 32 Meg x 4 x 4 banks MT46V64M8 - 16 Meg x 8 x 4 banks MT46V32M16 - 8 Meg x 16 x 4 banks
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PIN ASSIGNMENT (TOP VIEW) 66-Pin TSOP
x4 x8 x16 VDD VDD VDD NC DQ0 DQ0 VDDQ VDDQ VDDQ NC NC DQ1 DQ0 DQ1 DQ2 VSSQ VSSQ VssQ NC NC DQ3 NC DQ2 DQ4 VDDQ VDDQ VDDQ NC NC DQ5 DQ1 DQ3 DQ6 VSSQ VSSQ VssQ NC NC DQ7 NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD DNU DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
OPTIONS
MARKING
* Configuration 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 * Plastic Package - OCPL 66-pin TSOP (standard 22.3mm length) TG (400 mil width, 0.65mm pin pitch) * Timing - Cycle Time 7.5ns @ CL = 2 (DDR266B)1 -75Z -75 7.5ns @ CL = 2.5 (DDR266B)2 10ns @ CL = 2 (DDR200)2 -8 * Self Refresh Standard none Low Power L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing 2. Supports PC2100 modules with 2.5-3-3 timing 3. Supports PC1600 modules with 2-2-2 timing
x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
128 Meg x 4 Configuration Refresh Count Row Addressing BankAddressing Column Addressing 32 Meg x 4 x 4 banks 8K 8K(A0-A12) 4 (BA0, BA1) 4K(A0-A9,A11,A12)
64 Meg x 8 8K 8K(A0-A12) 4 (BA0, BA1) 2K(A0-A9, A11)
32 Meg x 16 8K 8K(A0-A12) 4 (BA0, BA1) 1K(A0-A9)
16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
KEY TIMING PARAMETERS
SPEED GRADE -75 -75 -8 CLOCK RATE CL = 2** 133 MHz 100 MHz 100 MHz CL = 2.5** 133 MHz 133 MHz 125 MHz DATA-OUT 2.5ns 2.5ns 3.4ns ACCESS 0.75ns 0.75ns 0.8ns DQS-DQ SKEW +0.5ns +0.5ns +0.6ns WINDOW* WINDOW
*Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75) **CL = CAS (Read) Latency
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
512Mb DDR SDRAM PART NUMBERS
(Note: xx= -75, -75Z, or -8) PART NUMBER MT46V128M4TG-xx MT46V128M4TG-xxL MT46V64M8TG-xx MT46V64M8TG-xxL MT46V32M16TG-xx MT46V32M16TG-xxL www..com CONFIGURATION 128 Meg x 4 128 Meg x 4 64 Meg x 8 64 Meg x 8 32 Meg x 16 32 Meg x 16 I/O DRIVE LEVEL Full Drive Full Drive Full Drive Full Drive Programmable Drive Programmable Drive REFRESH OPTION Standard Low Power Standard Low Power Standard Low Power
GENERAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quadbank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 512Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive strength outputs are SSTL_2, Class II compatible.
NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided in to two bytes--the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS; and for the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 128 Meg x 4 ............. Functional Block Diagram - 64 Meg x 8 ............... Functional Block Diagram - 32 Meg x 16 ............. Pin Descriptions ...................................................... Functional Description ......................................... Initialization ...................................................... Register Definition ............................................. Mode Register ............................................... Burst Length ............................................ www..com Burst Type ................................................ Read Latency ........................................... Operating Mode ...................................... Extended Mode Register ............................... DLL Enable/Disable ................................. Commands ............................................................ Truth Table 1 (Commands) ....................................... Truth Table 1A (DM Operation) ................................. Deselect .............................................................. No Operation (NOP) .......................................... Load Mode Register ........................................... Active ................................................................ Read ................................................................ Write ................................................................ Precharge ........................................................... Auto Precharge .................................................. Burst Terminate ................................................. Auto Refresh ...................................................... Self Refresh ......................................................... Operation .............................................................. Bank/Row Activation ....................................... Reads ................................................................ Read Burst .................................................... Consecutive Read Bursts .............................. Nonconsecutive Read Bursts ....................... Random Read Accesses ................................ Terminating a Read Burst ............................ Read to Write ............................................... Read to Precharge ......................................... Writes ................................................................ Write Burst .................................................... Consecutive Write to Write ......................... Nonconsecutive Write to Write .................. 4 5 6 7 9 9 9 9 9 10 11 11 12 12 13 13 13 14 14 14 14 14 14 14 14 14 15 15 16 16 17 18 19 20 21 23 24 25 26 27 28 29 Random Writes ............................................ Write to Read - Uninterrupting .................. Write to Read - Interrupting ....................... Write to Read - Odd, Interrupting ............. Write to Precharge - Uninterrupting .......... Write to Precharge - Interrupting ............... Write to Precharge - Odd, Interrupting ...... Precharge ........................................................... Power-Down ..................................................... Truth Table 2 (CKE) ................................................. Truth Table 3 (Current State, Same Bank) ..................... Truth Table 4 (Current State, Different Bank) ................. Operating Conditions Absolute Maximum Ratings .................................... DC Electrical and Operating Conditions ..................... AC Input Operating Conditions ........................... Clock Input Operating Conditions ....................... Capacitance - x4, x8 .............................................. IDD Specifications and Conditions - x4, x8 ........... Capacitance - x16 .................................................. IDD Specifications and Conditions - x16 ............... AC Electrical Characteristics (Timing Table) .......... Slew Rate Derating Table ....................................... Data Valid Window Derating ............................... Voltage and Timing Waveforms Nominal Output Drive Curves ......................... Reduced Output Drive Curves (x16 only) ........ Output Timing - tDQSQ and tQH - x4, x8 ...... Output Timing - tDQSQ and tQH - x16 .......... Output Timing - tAC and tDQSCK ................. Input Timing ..................................................... Input Voltage .................................................... Initialize and Load Mode Registers .................. Power-Down Mode .......................................... Auto Refresh Mode ........................................... Self Refresh Mode ............................................. Reads Bank Read - Without Auto Precharge ........ Bank Read - With Auto Precharge .............. Writes Bank Write - Without Auto Precharge ....... Bank Write - With Auto Precharge ............. Write - DM Operation ................................ 66-pin TSOP (TG) dimensions ............................... 30 31 32 33 34 35 36 37 37 38 39 41
43 43 43 44 45 45 46 46 47 48 52 53 54 55 56 57 57 58 59 60 61 62 63 64 65 66 67 68
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM 128 Meg x 4
CKE CK# CK CS# CONTROL LOGIC BANK3 BANK2 BANK1
CAS# RAS#
COMMAND DECODE
www..com WE#
MODE REGISTERS
REFRESH 13 COUNTER
13 13
ROWADDRESS MUX
13
BANK0 ROWADDRESS LATCH & DECODER
8192
BANK0 MEMORY ARRAY (8,192 x 2,048 x 8)
4 8 READ LATCH MUX 4 DQS GENERATOR COL0 4
CK
DATA
DLL
SENSE AMPLIFIERS 16,384
DRVRS 1 DQ0 DQ3, DM DQS DQS 1 1 1 2 4 8 4 DATA 4 4 4 RCVRS 1
2
I/O GATING DM MASK LOGIC
BANK CONTROL LOGIC
8 1 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS
A0-A12, BA0, BA1
15
ADDRESS REGISTER
2
2048 (x8)
8
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
11
12
CK COL0
1
1
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM 64 Meg x 8
CKE CK# CK CS# CONTROL LOGIC BANK3 BANK2 BANK1
CAS# RAS#
COMMAND DECODE
www..com WE#
MODE REGISTERS
REFRESH 13 COUNTER
13 13
ROWADDRESS MUX
13
BANK0 ROWADDRESS LATCH & DECODER
8192
BANK0 MEMORY ARRAY (8192 x 1024 x 16)
8 16 READ LATCH MUX 8 DQS GENERATOR COL0 8
CK
DATA
DLL
SENSE AMPLIFIERS 16,384
DRVRS 1 DQ0 DQ7, DM DQS DQS 1 1 1 2 8 16 8 DATA 8 8 8 RCVRS 1
2
I/O GATING DM MASK LOGIC
BANK CONTROL LOGIC
16 1 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS
A0-A12, BA0, BA1
15
ADDRESS REGISTER
2
1024 (x16)
16
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
10
11
CK COL0
1
1
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM 32 Meg x 16
CKE CK# CK
WE# CAS# RAS#
COMMAND DECODE
www..com CS#
CONTROL LOGIC BANK3 BANK2 REFRESH COUNTER 13 BANK1
MODE REGISTERS
13 13
ROWADDRESS MUX
13
BANK0 ROWADDRESS LATCH & DECODER
8192
BANK0 MEMORY ARRAY (8,192 x 512 x 32)
16 32 READ LATCH MUX 16 DQS GENERATOR COL0 16
CK
DATA
DLL
SENSE AMPLIFIERS 16,384
DRVRS 2 DQ0 DQ15, LDM, UDM LDQS UDQS 2 2 4 16 32 16 DATA 16 16 16 RCVRS 2
2 A0-A12, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
I/O GATING DM MASK LOGIC
32 2 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS 2
DQS
15
2
512 (x32)
32
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 9
10
CK COL0
2
1
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
PIN DESCRIPTIONS
TSOP PIN NUMBERS 45, 46 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8 Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63 are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 for x4).
44
CKE
Input
www..com
24
CS#
Input
23, 22, 21 47 20, 47
RAS#, CAS#, WE# DM LDM, UDM
Input Input
26, 27 29-32, 35-40, 28, 41, 42
BA0, BA1 A0-A12
Input Input
2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65
DQ0-15
I/O
(continued on next page)
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
PIN DESCRIPTIONS (continued)
TSOP PIN NUMBERS 2, 5, 8, 11, 56, 59, 62, 65 5, 11, 56, 62 51 16, 51 SYMBOL DQ0-7 DQ0-3 DQS LDQS, UDQS TYPE I/O I/O I/O DESCRIPTION Data Input/Output: Data bus for x8 (2, 8, 59 and 65 are NC for x4). Data Input/Output: Data bus for x4. Data Strobe: Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8. Do Not Use: Must float to minimize noise. DQ Power Supply: +2.5V 0.2V. Isolated on the die for improved noise immunity. DQ Ground. Isolated on the die for improved noise immunity. Power Supply: +2.5V 0.2V. Ground. SSTL_2 reference voltage. No Connect: These pins should be left unconnected.
50
www..com
DNU VDDQ VSSQ VDD VSS VREF NC
- Supply Supply Supply Supply Supply -
3, 9, 15, 55, 61
6, 12, 52, 58, 64 1, 18, 33 34, 48, 66 49 14, 17, 19, 25, 43, 53
RESERVED NC PINS1
TSOP PIN NUMBERS 17 SYMBOL A13 TYPE I DESCRIPTION Address input for 1Gb devices.
NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed to be of importance.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
FUNCTIONAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM www..com consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. LECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.
Register Definition
MODE REGISTER The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 1. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESE-
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai www..com burst length is set to eight (where Ai is the when the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Table 1 Burst Definition
Burst Length Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
14 13 12 11 10 9 8 Operating Mode 0* 0* * M14 and M13 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register).
7
6543210 CAS Latency BT Burst Length
Mode Register (Mx)
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
2
4
M3 0 1
Burst Type Sequential Interleaved
8
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved
M12 M11 M10 M9 M8 M7 0 0 0 0 0 0 0 0 0 1 0 0 -
M6-M0 Valid Valid -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
Figure 1 Mode Register Definition
NOTE: 1. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 2.5 clocks, as shown in Figure 2. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 2 indicates the operating frequencies at which each CAS latency setting can be used. www..com Reserved states should not be used as unknown operation or incompatibility with future versions may result.
T0 CK# CK COMMAND
READ NOP NOP NOP
Table 2 CAS Latency (CL)
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -75Z -75 -8 CL = 2 75 f 133 75 f 100 75 f 100 CL = 2.5 75 f 133 75 f 133 75 f 125
T1
T2
T2n
T3
T3n
CL = 2 DQS DQ T0 T1 T2 T2n T3 T3n
CK# CK COMMAND
READ
NOP
NOP
NOP
CL = 2.5 DQS DQ
Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ TRANSITIONING DATA DON'T CARE
Figure 2 CAS Latency
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EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enwww..com the DLL should always be followed by a LOAD abling of MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Output Drive Strength The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54% of the SSTL2, Class II drive strength. The Micron (32Meg x16) device supports a programmable drive strength option. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
0 - BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11
4
3
2
1
0
QFC# DS DLL
Extended Mode Register (Ex)
E0 0 1 E12 0 1 E23 0 -
DLL Enable Disable Drive Strength Normal Reduced
QFC# Function Disabled Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 -
E2, E1, E0 Valid -
Operating Mode Reserved Reserved
NOTE: 1. E14 and E13 (BA0 and BA1) must be "1, 0" to select the Extended Mode Register (vs. the base Mode Register). 2. The reduced drive strength option is not supported on the x4 and x8 versions, and is only available on the x16 version. 3. The QFC# option is not supported.
Figure 3 Extended Mode Register Definition
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COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
TRUTH TABLE 1 - COMMANDS
(Note: 1) NAME (FUNCTION) www..com DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# H L L L L L L L L RAS# X H L H H H L L L CAS# X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code NOTES 9 9 3 4 4 8 5 6, 7 2
TRUTH TABLE 1A - DM OPERATION
(Note: 10) NAME (FUNCTION) Write Enable Write Inhibit DM L H DQs Valid X NOTES
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the opcode to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 9 for x16, 9,11 for x8, and 9, 11, 12 for x4); A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data.
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations www..com progress are not affected. already in LOAD MODE REGISTER The mode registers are loaded via inputs A0-A12. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11, and 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 9 for x16; 9 and 11 for x8; or 9, 11, and 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed.
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BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. The open page which the READ burst was terminated from remains open. AUTO REFRESH www..com AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an AUTO REFRESH command. The 512Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH command can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125s (70.3s). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
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Operations
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 4. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the www..com next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 5, which covers any case where 2 < tRCD (MIN)/ tCK 3. (Figure 5 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A12
RA
BA0,1
BA
RA = Row Address BA = Bank Address
Figure 4 Activating a Specific Row in a Specific Bank
T0 CK# CK COMMAND
ACT
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
ACT
NOP
NOP
RD/WR
NOP
A0-A12
Row
Row
Col
BA0, BA1
Bank x
Bank y
Bank y
tRRD
tRCD
DON'T CARE
Figure 5 Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK 3
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READs READ bursts are initiated with a READ command, as shown in Figure 6. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element www..com starting column address will be available folfrom the lowing the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure 7 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last dataout element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid dataout skew), tQH (data-out window hold), the valid data window are depicted in Figure 27. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 28. Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 8. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 9. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 10. CK# CK CKE CS# HIGH
RAS# CAS#
WE# x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 x8: A12 x16: A11, A12
EN AP CA
A10
DIS AP
BA0,1
BA
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE
Figure 6 READ Command
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T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T5
CL = 2
www..comDQS
DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP
DO n
T1
T2
T2n
T3
T3n
T4
T5
NOP
NOP
NOP
CL = 2.5 DQS DQ
DO n
NOTE: 1. DO n = data-out from column n. DON'T CARE TRANSITIONING DATA 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 7 READ Burst
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T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2 DQS
www..com
DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP READ Bank, Col b
DO n
DO b
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
NOP
NOP
NOP
CL = 2.5 DQS DQ
DO n DO b
DON'T CARE NOTE: 1. 2. 3. 4. 5. 6.
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies only when READ commands are issued to same device.
Figure 8 Consecutive READ Bursts
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T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T5
T5n
T6
CL = 2 DQS
www..com
DQ T0 T1 T2
DO n
DO b
T2n
T3
T3n
T4
T5
T5n
T6
CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP
CL = 2.5 DQS DQ
DO n DO b
NOTE: 1. 2. 3. 4. 5. 6.
DON'T CARE TRANSITIONING DATA DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies when READ commands are issued to different devices or nonconsecutive READs.
Figure 9 Nonconsecutive READ Bursts
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T0 CK# CK COMMAND ADDRESS
READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2 DQS
www..com
DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n READ Bank, Col x READ Bank, Col b
DO n
DO n'
DO x
DO x'
DO b
DO b'
DO g
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
READ Bank, Col g
NOP
NOP
CL = 2.5 DQS DQ
DO n DO n' DO x DO x' DO b DO b'
DON'T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DO n (or x or b or g) = data-out from column n (or column x or column b or column g). Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous). n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively. READs are to an active row in any bank. Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 10 Random READ Accesses
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READs (continued) Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can www..com If truncation is necessary, the BURST TERbe issued. MINATE command must be used, as shown in Figure 12. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.) A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 13. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements.
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T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST5 NOP NOP NOP NOP
T1
T2
T2n
T3
T4
T5
CL = 2 DQS
www..com
DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST5 NOP
DO n
T1
T2
T2n
T3
T4
T5
NOP
NOP
NOP
CL = 2.5 DQS DQ NOTE: 1. 2. 3. 4. 5.
DO n
DO n = data-out from column n. DON'T CARE TRANSITIONING DATA Burst length = 4. Subsequent element of data-out appears in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. BST = BURST TERMINATE command, page remains open.
Figure 11 Terminating a READ Burst
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T0 CK# CK COMMAND ADDRESS
READ Bank, Col n BST7 NOP WRITE Bank, Col b NOP NOP
T1
T2
T2n
T3
T4
T4n
T5
T5n
CL = 2
www..com
tDQSS (MIN)
DQS DQ DM T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST7 NOP NOP WRITE NOP DO n DI b
T1
T2
T2n
T3
T4
T5
T5n
CL = 2.5 DQS DQ DM
DO n
tDQSS (MIN)
DI b
NOTE: 1. DO n = data-out from column n. DON'T CARE TRANSITIONING DATA 2. DI b = data-in from column b. 3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the BST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC, tDQSCK, and tDQSQ. 7. BST = BURST TERMINATE command, page remains open.
Figure 12 READ to WRITE
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND6 ADDRESS
READ Bank a, Col n NOP PRE Bank a, (a or all) NOP NOP ACT Bank a, Row
T1
T2
T2n
T3
T3n
T4
T5
CL = 2 DQS
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tRP
DQ T0 CK# CK COMMAND6 ADDRESS
READ Bank a, Col n NOP PRE
DO n
T1
T2
T2n
T3
T3n
T4
T5
NOP
NOP
ACT Bank a, Row
Bank a, (a or all)
CL = 2.5 DQS DQ
DO n
tRP
NOTE: 1. 2. 3. 4. 5. 6.
DON'T CARE TRANSITIONING DATA DO n = data-out from column n. Burst length = 4, or an interrupted burst of 8. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out. A READ command with AUTO-PRECHARGE enabled would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL / 2. 7. PRE = PRECHARGE command; ACT = ACTIVE command.
Figure 13 READ to PRECHARGE
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in elewww..com be registered on the first rising edge of DQS ment will following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 15 shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Figure 16 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 17. Full-speed random write accesses within a page or pages can be performed as shown in Figure 18. Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met as shown in Figure 19. Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 20. Note that only the data-in pairs that are registered
CK# CK CKE CS# RAS# CAS# HIGH
WE# x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 x8: A12 x16:A11, A12
EN AP
CA
A10
DIS AP
BA0,1
BA
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE
Figure 14 WRITE Command
prior to the tWTR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figure 21. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 22. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figures 23 and 24. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figures 23 and 24. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND ADDRESS
tDQSS (NOM)
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T1
T2
T2n
T3
WRITE Bank a, Col b
NOP
NOP
NOP
DQS DQ DM
tDQSS (MIN)
tDQSS
DI b
DQS DQ DM
tDQSS (MAX)
tDQSS
DI b
DQS DQ DM
tDQSS
DI b
DON'T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled).
Figure 15 WRITE Burst
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T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5
WRITE
NOP
WRITE
NOP
NOP
NOP
ADDRESS
www..com tDQSS (NOM)
Bank, Col b tDQSS
Bank, Col n
DQS
DI b DI n
DQ DM
DON'T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank.
Figure 16 Consecutive WRITE to WRITE
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T0 CK# CK COMMAND T1 T1n T2 T2n T3 T4 T4n T5 T5n
WRITE
NOP
NOP
WRITE
NOP
NOP
ADDRESS
www..com tDQSS (NOM)
Bank, Col b tDQSS
Bank, Col n
DQS
DI b DI n
DQ DM
DON'T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank.
FIGURE 17 Nonconsecutive WRITE to WRITE
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n
WRITE
WRITE
WRITE
WRITE
WRITE
NOP
ADDRESS
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Bank, Col b
Bank, Col x
Bank, Col n
Bank, Col a
Bank, Col g
tDQSS (NOM)
DQS
DI b DI b' DI x DI x' DI n DI n' DI a DI a' DI g DI g'
DQ DM
DON'T CARE NOTE: 1. 2. 3. 4.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. b', etc. = the next data-in following DI b, etc., according to the programmed burst order. Programmed burst length = 2, 4, or 8 in cases shown. Each WRITE command may be to any bank.
Figure 18 Random WRITE Cycles
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND
WRITE NOP NOP NOP tWTR READ NOP NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS www..com DQ DM
tDQSS (MIN) tDQSS DI b DI n
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DI n
CL = 2
DQS DQ DM DON'T CARE TRANSITIONING DATA DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. tWTR is referenced from the first positive CK edge after the last data-in pair. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled).
DI b DI n
NOTE: 1. 2. 3. 4. 5.
Figure 19 WRITE to READ - Uninterrupting
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND
WRITE NOP NOP tWTR READ NOP NOP NOP
T1
T1n
T2
T2n
T3
T4
T5
T5n
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
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DQS DQ DM
DI b DI n
tDQSS (MIN)
tDQSS
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DI n
CL = 2
DQS DQ DM DON'T CARE TRANSITIONING DATA DI b = data-in for column b. An interrupted burst of 4 or 8 is shown; two data elements are written. One subsequent element of data-in is applied in the programmed order following DI b. tWTR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last two data elements.
DI b DI n
NOTE: 1. 2. 3. 4. 5. 6. 7.
Figure 20 WRITE to READ - Interrupting
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T0 CK# CK COMMAND
WRITE NOP NOP tWTR READ NOP NOP NOP
T1
T1n
T2
T2n
T3
T4
T5
T5n
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
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DQS DQ DM
DI b DI n
tDQSS (MIN)
tDQSS
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DI n
CL = 2
DQS DQ DM DON'T CARE TRANSITIONING DATA DI b = data-in for column b. An interrupted burst of 4 is shown; one data element is written. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T1n, T2, and T2n (nominal case) to register DM. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last four data elements.
DI b DI n
NOTE: 1. 2. 3. 4. 5. 6.
Figure 21 WRITE to READ - Odd Number of Data, Interrupting
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND
WRITE NOP NOP NOP tWR NOP PRE7 tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS www..com DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM DON'T CARE TRANSITIONING DATA DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command.
DI b
NOTE: 1. 2. 3. 4. 5.
Figure 22 WRITE to PRECHARGE - Uninterrupting
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T0 CK# CK COMMAND
WRITE NOP NOP tWR NOP PRE9 NOP tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS www..com DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM DON'T CARE TRANSITIONING DATA DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 4 is shown; two data elements are written. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command.
DI b
NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
Figure 23 WRITE to Precharge - Interrupting
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512Mb: x4, x8, x16 DDR SDRAM
T0 CK# CK COMMAND
WRITE NOP NOP tWR NOP PRE9 NOP tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS www..com DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM
DI b
DON'T CARE NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
TRANSITIONING DATA
DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 4 is shown; one data element is written. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T1n, T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command.
Figure 24 WRITE to PRECHARGE Odd Number of Data, Interrupting
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PRECHARGE The PRECHARGE command (Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10
CK# CK CKE CS# HIGH
determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN (CKE NOT ACTIVE) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress: from the issuing of a READ or WRITE command until completion of the burst. Thus a clock suspend is not supported. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined when the Write Postamble is satisfied. Power-down (Figure 26) is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum power savings, the DLL is frozen during precharge power-down. Exiting power-down requires the device to be at the same voltage and frequency as when it entered power-down. However, power-down duration is limited by the refresh requirements of the device (tREFC). While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are "Don't Care." The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
www..com
RAS#
CAS#
WE#
A0-A9, A11, A12
ALL BANKS
A10
ONE BANK
BA0,1
BA
BA = Bank Address (if A10 is LOW; otherwise "Don't Care") DON'T CARE
Figure 25 PRECHARGE Command
T0 CK# CK
tIS
T1
T2 ( (
Ta0
Ta1
Ta2
)) (( ))
tIS
CKE
(( ))
COMMAND
VALID
NOP
(( )) (( ))
NOP
VALID
No READ/WRITE access in progress
Enter power-down mode
Exit power-down mode DON'T CARE
Figure 26 Power-Down
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512Mb: x4, x8, x16 DDR SDRAM
TRUTH TABLE 2 - CKE
(Notes: 1-4) CKEn-1 CKEn L L H
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CURRENT STATE Power-Down Self Refresh Power-Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle
COMMAND n X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH See Truth Table 3
ACTION n Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry
NOTES
L H L
5
H
NOTE: 1. 2. 3. 4. 5.
H
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200 clock cycles is needed before applying a READ command for the DLL to lock.
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TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any H L L Idle
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COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE)
NOTES
X H L L L H H L H H L H H H L
X H H L L L L H L L H H L L H
X H H H L H L L H L L L H L L
L L L L L L L L L L L L
7 7 10 10 8 10 10, 12 8 9 10, 11 10 8, 11
Row Active Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled)
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. www..com bank-specific; requires that all banks are idle, and bursts are not in progress. 7. Not 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. 10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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512Mb: x4, x8, x16 DDR SDRAM
TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating,
www..com Active, or
CS# RAS# CAS# WE# H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L
COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE
NOTES
7 7
Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (With AutoPrecharge) Write (With AutoPrecharge)
7 7, 9
7, 8 7
7, 3a 7, 9, 3a
7, 3a 7, 3a
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. (Notes continued on next page)
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NOTE (continued): 3.Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read with Auto www..com Precharge Enabled: See following text - 3a Write with Auto Precharge Enabled: See following text - 3a 3a. The read with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends,with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. To Command READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE Minimum delay (with concurrent auto precharge) [1 + (BL/2)] tCK + tWTR (BL/2) tCK 1 tCK 1 tCK (BL/2) * tCK [CLRU + (BL/2)] tCK 1 tCK 1 tCK
From Command WRITE w/AP
READ w/AP
CLRU = CAS Latency (CL) rounded up to the next integer BL = Bust Length 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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512Mb: x4, x8, x16 DDR SDRAM
ABSOLUTE MAXIMUM RATINGS*
VDD Supply Voltage Relative to VSS ............. -1V to +3.6V VDDQ Supply Voltage Relative to VSS .......... -1V to +3.6V VREF and Inputs Voltage Relative to VSS ........ -1V to +3.6V I/O Pins Voltage Relative to VSS ........ -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) .... 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ........................................................ 1W Short Circuit Output Current ................................. 50mA
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*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1-5, 16; notes appear on pages 50-53) (0C TA +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x4, x8, x16 High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) II IOZ MIN 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -2 -5 MAX 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 2 5 UNITS NOTES V V V V V V A A 36, 41 36, 41, 44 6, 44 7, 44 28 28
IOH IOL IOHR IOLR
-16.8 16.8 -9 9
- - - -
mA mA
37, 39
mA 38, 39 mA
AC INPUT OPERATING CONDITIONS
(Notes: 1-5, 14, 16; notes appear on pages 50-53) (0C TA +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) MIN VREF + 0.310 - 0.49 x VDDQ MAX - VREF - 0.310 0.51 x VDDQ UNITS V V V NOTES 14, 28, 40 14, 28, 40 6
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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VDDQ (2.3V minimum)
1 VOH(MIN) (1.670V for SSTL2 termination) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V VIHAC
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1.400V VIHDC
1.300V 1.275V 1.250V 1.225V 1.200V
VREF +AC Noise VREF +DC Error VREF -DC Error VREF -AC Noise
1.100V
VILDC
0.940V VINAC - Provides margin between VOL (MAX) and VILAC VOL (MAX) (0.83V2 for SSTL2 termination)
VILAC
Receiver
VSSQ
NOTE: 1. VOH (MIN) with test load is 1.927V 2. VOL (MAX) with test load is 0.373V 3. Numbers in diagram reflect nomimal values utilizing circuit below.
VTT 25 25 Reference Point
Transmitter
Figure 27 Input Voltage Waveform
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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CLOCK INPUT OPERATING CONDITIONS
(Notes: 1-5, 15, 16, 30; notes appear on pages 50-53) (0C TA + 70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK#
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SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC)
MIN 1.15 -0.3 0.36 0.7 0.5 x VDDQ - 0.2
MAX 1.35 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.2
UNITS V V V V V
NOTES 6, 9 6 6, 8 8 9
2.80v
CK
Maximum Clock Level
5
1.45v 1.25v 1.05v
X
VMP (DC)
1
VIX (AC)
2
VID (DC) 4 VID (AC)
3
X
CK#
- 0.30v
Minimum Clock Level
5
NOTE:
1. This provides a minimum of 1.15v to a maximum of 1.35v, and is always half of VDDQ. 2. CK and CK# must cross in this region. 3. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC) 4. CK and CK# must have a minimum 700mv peak to peak swing. 5. CK or CK# may not be more positive than VDDQ + 0.3v or more negative than Vss - 0.3v. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values.
FIGURE 28 - SSTL_2 CLOCK INPUT
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CAPACITANCE (x4, x8)
(Note: 13; notes appear on pages 50-53) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address
www..com Input Capacitance: CK, CK#
SYMBOL DCIO DCI1 DCI2 CIO CI1 CI2 CI3
MIN - - - 4.0 2.0 2.0 2.0
MAX 0.50 0.50 0.25 5.0 3.0 3.0 3.0
UNITS pF pF pF pF pF pF pF
NOTES 24 29 29
Input Capacitance: CKE
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(Notes: 1-5, 10, 12, 14; notes appear on pages 50-53) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) MAX PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; = tCK = tCK(MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK(MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;One bank; Active-Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE 0.2V
tRC tRC tRC tRC(MIN);
SYMBOL -75/-75Z IDD0 TBD
-8
UNITS NOTES mA 22, 48
TBD
IDD1
TBD
TBD
mA
22, 48
IDD2P IDD2F
3 35
3 30
mA mA
23, 32 50 51
IDD3P IDD3N
3 35
3 30
mA mA
23, 32 50 22
IDD4R
TBD
TBD
mA 22, 48
IDD4W
TBD
TBD
mA
22
= 7.8125s = tRC(MIN)
IDD5 IDD6 IDD7 IDD7 IDD8
6 TBD TBD TBD TBD
6 TBD TBD TBD TBD
mA mA mA mA mA
27,50 22,50 11 11 22, 49
Standard Low power (L)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC = tRC(MIN); tCK = tRC(MIN); Address and control inputs change only during Active READ, or WRITE commands.
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CAPACITANCE (x16)
(Note: 13; notes appear on pages 50-53) PARAMETER Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address www..com Input Capacitance: CK, CK# Input Capacitance: CKE SYMBOL DCIOL DCIOU DCI1 DCI2 CIO CI1 CI2 CI3 MIN - - - - 4.0 2.0 2.0 2.0 MAX 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0 UNITS pF pF pF pF pF pF pF pF NOTES 24 24 29 29
IDD SPECIFICATIONS AND CONDITIONS (x16)
(Notes: 1-5, 10, 12, 14; notes appear on pages 50-53) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) MAX PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; = tCK = tCK(MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK(MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE 0.2V
tRC tRC tRC tRC(MIN);
SYMBOL -75/-75Z IDD0 TBD
-8
UNITS NOTES mA 22, 48
TBD
IDD1
TBD
TBD
mA
22, 48
IDD2P IDD2F
3 40
3 35
mA mA
23, 32 50 51
IDD3P IDD3N
3 35
3 30
mA mA
23, 32 50 22
IDD4R
TBD
TBD
mA
22, 48
IDD4W
TBD
TBD
mA
22
= 7.8125s = 7.8125s
IDD5 IDD5 IDD6 IDD7 IDD7
6 6 TBD TBD TBD
6 6 TBD TBD TBD
mA mA mA mA mA
27,50 27,50 11 11 22, 49
Standard Low power (L)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with , tRC = tRC(MIN); tCK = tRC(MIN); Address and control inputs change only during Active READ, or WRITE commands.
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear on pages 50-53) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM input hold time relative to DQS
www..comDM input setup time relative to DQS DQ and
CL = 2.5 CL = 2
DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
SYMBOL tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIH F t IS F tIH S tIH S tMRD tQH
tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR
MIN -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35
-75Z MAX +0.75 0.55 0.55 13 13
+0.75
MIN -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.8 0.35 0.35
-75 MAX +0.75 0.55 0.55 13 13
-8 MIN -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 0.75 0.2 0.2 tCH,tCL -0.8 1.1 1.1 1.1 1.1 16 MAX +0.8 0.55 0.55 13 13 UNITS ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK NOTES 30 30 45, 52 45, 52 26, 31 26, 31 31
+0.75
+0.8
0.75 0.2 0.2 tCH,tCL -0.75 .90 .90 1 1 15
0.5 1.25
0.75 0.2 0.2 tCH,tCL -0.75 .90 .90 1 1 15
0.5 1.25
0.6 1.25
25, 26
+0.75
+0.75
+0.8
34 18,42 18,43 14 14 14 14 25, 26
na
tREFC tREFI tVTD tXSNR tXSRD
40 20 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 7.8 0 75 200
tHP -tQHS 0.75 120,000
40 20 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 7.8 0 75 200
tHP -tQHS 0.75 120,000
40 20 70 80 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 7.8 0 80 200
tHP -tQHS 1 120,000
35 46 50
42
20, 21 19
25 23 23
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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SLEW RATE DERATING VALUES
(Note: 14; notes appear on pages 50-53) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
ADDRESS / COMMAND SPEED -75Z, -75 -75Z, -75 -75Z, -75 -75Z, -75
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SLEW RATE 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns
tIS
tIH
UNITS ns ns ns ns ns ns ns ns
1 1.05 1.10 1.15 1.1 1.15 1.20 1.25
1 1 1 1 1.1 1.1 1.1 1.1
-8 -8 -8 -8
SLEW RATE DERATING VALUES
(Note: 31; notes appear on pages 50-53) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
DQ, DM, DQS SPEED -75Z, -75 -75Z, -75 -75Z, -75 -75Z, -75 -8 -8 -8 -8 SLEW RATE 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns 0.500V / ns 0.400V / ns 0.300V / ns 0.200V / ns
tDS tDH
UNITS ns ns ns ns ns ns ns ns
0.50 0.55 0.60 0.65 0.60 0.65 0.70 0.75
0.50 0.55 0.60 0.65 0.60 0.65 0.70 0.75
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NOTES
1. 2. All voltages referenced to VSS. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Outputs measured with equivalent load: 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS(MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an
3.
VTT
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Output (VOUT)
50 Reference Point 30pF
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -75Z and -8, CL = 2.5 for -75 with the outputs open. 11. Enables on-chip refresh and address counters.
4.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
50
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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512Mb: x4, x8, x16 DDR SDRAM
NOTES (continued)
average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and www..com t tQH ( HP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns if measured differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4% if CKE is not active while any bank is active.
3.8 3.750 3.6 3.400 3.700
DERATING DATA VALID WINDOW (tQH - tDQSQ)
3.650
3.600 3.550 3.500 3.450 3.400 3.200 3.150 3.100 3.050 3.000 2.950 2.900 3.350 3.300 3.250
3.4
3.350
3.300 3.250
3.2
---- -75 @ u
3.0 ns
---- -8 @ tCK = 10ns ---- -75 @ tCK = 7.5ns n ---- -8 @ tCK = 8ns l
#
tCK
= 10ns
2.8
2.6
2.500
2.463
2.425
2.4
2.388
2.350
2.313
2.275
2.238
2.200
2.2
2.163
2.125
2.0
1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55
Clock Duty Cycle
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NOTES (continued)
33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHPmin is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 35. READs and WRITEs with autoprecharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. www..com 36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b )The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d )The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 volt. 38.Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b ) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d ) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
Figure B Pull-Up Characteristics
160 140 120
Figure A Pull-Down Characteristics
0 -20 -40 -60
100 IOUT (mA) 80 60 40 20
IOUT (mA)
0.0 0.5 1.0 VOUT (V) 1.5 2.0 2.5
-80 -100 -120 -140 -160 -180
0
-200 0.0 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V)
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NOTES (continued)
39. The voltage levels used are derived from a minimum VDD level and the refernced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be www..com greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZmax and the last DVW. tHZ(MAX) will prevail over tDQSCK(MAX) + tRPST(MAX) condition. 43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. tLZ(MIN) will prevail over a tDQSCK(MIN) + tRPRE(MAX) condition. 44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. Reserved for future use. 47. Reserved for future use. 48. Random addressing changing 50% of data changing at every transfer. 49. Random addressing changing 100% of data changing at every transfer. 50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset, and followed by 200 clock cycles.
80 70 60
Figure C Pull-Down Characteristics
0 -5 -10 -15
Figure D Pull-Up Characteristics
50 IOUT (mA) 40 30 20 10
IOUT (mA)
0.0 0.5 1.0 VOUT (V) 1.5 2.0 2.5
-20 -25 -30 -35 -40 -45
0
-50 0.0 0.2 0.4 0.6 0.8 1.0 VDDQ - VOUT (V)
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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NORMAL OUTPUT DRIVE CHARACTERISTICS
VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 www..com 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) NOMINAL NOMINAL NOMINAL NOMINAL LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.8 63.3 63.8 64.1 64.6 64.8 65.0 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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REDUCED OUTPUT DRIVE CHARACTERISTICS
PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL (V) LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 0.3 0.4 www..com 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 6.9 10.3 13.6 16.9 19.9 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 -7.8 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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T1 T2 T2n T3 T3n T4
CK# CK
tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3 tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3
DQS1 QFC#
www..com
DQ (Last data valid) DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)
tQH4 tQH4 tQH4 tQH4
DQ (Last data valid) DQ (First data no longer valid)
T2 T2
T2n T2n
T3 T3
T3n T3n
All DQs and DQS, collectively6 Earliest signal transition Latest signal transition
T2
T2n
T3
T3n
Data Valid window
Data Valid window
Data Valid window
Data Valid window
NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS," at T3 is a "nominal DQS," and at T3n is a "late DQS" 2. For a x4, only two DQs apply. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs . 4. tQH is derived from tHP : tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
Figure 29 x4, x8 Data Output Timing - tDQSQ, tQH and Data Valid Window
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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512Mb: x4, x8, x16 DDR SDRAM
CK# CK
T1 T2 T2n T3 T3n T4
tHP5
tHP5 tDQSQ3
tHP5
tHP5 tDQSQ3
tHP5 tDQSQ3
tHP5 tDQSQ3
LDQS1 DQ (Last data valid)2 DQ2 DQ2 DQ2 DQ2 www..com DQ2 DQ2 DQ (First data no longer valid)2
tQH4 tQH4 tQH4 tQH4
Lower Byte
DQ (Last data valid)2 DQ (First data no longer valid)2 DQ0 - DQ7 and LDQS, collectively6
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
UDQS1 DQ (Last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7
tQH4 tQH4 tQH4 tQH4
Upper Byte
DQ (Last data valid)7 DQ (First data no longer valid)7 DQ8 - DQ15 and UDQS, collectively6
T2 T2 T2 Data Valid window
T2n T2n T2n Data Valid window
T3 T3 T3
T3n T3n T3n
Data Valid Data Valid window window
NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. 2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs .
4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
Figure 29 A x16 Data Output Timing - tDQSQ, tQH and Data Valid Window
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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T07 CK# CK tLZ(MIN) tRPRE DQS, or LDQS/UDQS2 DQ (Last data valid) T2 T2 T2 tLZ(MIN) T2n T2n T2n T3 T3 T3 T3n T3n T3n T4 T4 T4 T4n T4n T4n T5 T5 T5 T5n T5n T5n tDQSCK1(MAX) tDQSCK1(MIN) tDQSCK1(MAX) tHZ(MAX) tDQSCK1(MIN) tRPST T1 T2 T2n T3 T3n T4 T4n T5 T5n T6
www..com
DQ (First data valid) All DQs collectively3
NOTE: 1. 2. 3. 4. 5. 6. 7.
tHZ(MAX) tDQSCK is the DQS output window relative to CK and is the"long term" component of DQS skew. DQs transitioning after DQS transition define tDQSQ window. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK, and is the"long term" component of DQ skew. tLZ(MIN) and tAC(MIN) are the first valid signal transition. tHZ(MAX ,and tAC(MAX) are the latest valid signal transition. READ command with CL = 2 issued at T0.
tAC4(MIN)
tAC4(MAX)
Figure 30 Data Output Timing - tAC and tDQSCK
T03 CK# CK tDQSS DQS tWPRES tWPRE DQ DM tDS tDH DI b tDQSL tDQSH tWPST tDSH1 tDSS2 tDSH1 tDSS2 T1 T1n T2 T2n T3
TRANSITIONING DATA NOTE: 1. tDSH(MIN) generally occurs during tDQSS(MIN). 2. tDSS(MIN) generally occurs during tDQSS(MAX). DON'T CARE 3. WRITE command issued at T0. 4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
Figure 31 Data Input Timing
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
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512Mb: x4, x8, x16 DDR SDRAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
VDDQ VTT1 VREF
tVTD1
T0 CK# CK
(( )) (( ))
T1
(( )) (( ))
T2
(( )) (( ))
Ta0
(( )) (( ))
Tb0
(( )) (( ))
Tc0
(( )) (( ))
Td0
(( )) (( ))
Te0
tCH tIS tIH
tCL
www..com
LVCMOS CKE LOW LEVEL
(( ))
(( )) (( ))
tIS COMMAND
6
tIH
PRE tCK
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
NOP
LMR
LMR
PRE
AR
AR
ACT5
DM
tIS A0-A9, A11, A12
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
tIH
(( )) (( )) (( )) (( )) (( )) (( ))
CODE
CODE
(( )) (( )) ( ( ALL BANKS )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
RA
ALL BANKS
tIS
(( )) (( )) (( )) (( ))
tIH
CODE
A10
CODE
RA
tIS
tIH
tIS
tIH
BA0 = L, BA1 = L
(( )) (( ))
tIS
tIH
BA0, BA1
BA0 = H, BA1 = L
BA
DQS DQ
High-Z High-Z
(( )) (( ))
(( )) (( ))
(( )) (( )) tMRD tRP
(( )) (( ))
(( )) (( )) tRFC
(( )) (( )) tRFC5
T = 200s Power-up: VDD and CK stable tRP tMRD Load Extended Mode Register
200 cycles of CK3 Load Mode Register2 DON'T CARE
NOTE: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VDDQ, VDDQ, VTT and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H. 3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued. 4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0. 5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank. 6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, Bank Address
TIMING PARAMETERS
SYMBOL
tCH tCL tCK (2.5) tCK (2) tIH
-75Z MIN MAX 0.45 0.45 7.5 7.5 1 0.55 0.55 13 13
MIN 0.45 0.45 7.5 10 1
-75 MAX 0.55 0.55 13 13
-8 MIN 0.45 0.45 8 10 1.1 MAX 0.55 0.55 13 13 UNITS
tCK tCK
SYMBOL tIS tMRD
tRFC tRP tVTD
-75Z MIN MAX 1 15 75 20 0
MIN 1 15 75 20 0
-75 MAX
-8 MIN 1.1 16 80 20 0 MAX UNITS ns ns ns ns ns
ns ns ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
59
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
POWER-DOWN MODE
T0 CK# CK
tIS tIH tCK tIS
(( ))
T1
T2
tCH
tCL
(( )) (( ))
Ta0
Ta1
Ta2
tIS
CKE
www..com
tIS
tIH NOP
COMMAND
VALID1 tIS tIH
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
NOP
VALID
ADDR
VALID
VALID
DQS
DQ
DM
tREFC
Enter 2 Power-Down Mode
Exit Power-Down Mode DON'T CARE
NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 2. No column accesses are allowed to be in progress at the time power-down is entered.
TIMING PARAMETERS
SYMBOL tCH
tCL tCK (2.5)
-75Z MIN MAX 0.45 0.55 0.45 7.5 0.55 13
MIN 0.45 0.45 7.5
-75 MAX 0.55 0.55 13
-8 MIN 0.45 0.45 8 MAX 0.55 0.55 13 UNITS tCK
tCK
SYMBOL tCK (2)
tIH tIS
-75Z MIN MAX 7.5 13 1 1
MIN 10 1 1
-75 MAX 13
-8 MIN 10 1.1 1.1 MAX 13 UNITS ns ns ns
ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
60
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
AUTO REFRESH MODE
T0 CK# CK
tIS tIH tCK tCH VALID tIS tIH PRE NOP2 NOP2 AR tCL
T1
T2
T3
T4
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
Ta0
Ta1
(( )) (( )) (( )) (( ))
Tb0
Tb1
Tb2
CKE
VALID
COMMAND1
NOP 2
NOP2
AR5
(( )) (( )) (( )) (( ))
(( )) (( ))
NOP2
NOP2
ACT
www..com A0-A9,
A11, A121 A101
ONE BANK ALL BANKS
RA
(( )) (( ))
RA
tIS
tIH (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
BA0, BA11
Bank(s)3
(( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
BA
DQS4
DQ4
DM4
tRP
tRFC
tRFC5
DON'T CARE
NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 3. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 4. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown. 5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
TIMING PARAMETERS
SYMBOL
tCH tCL tCK (2.5) tCK (2)
-75Z MIN MAX 0.45 0.45 7.5 7.5 0.55 0.55 13 13
MIN 0.45 0.45 7.5 10
-75 MAX 0.55 0.55 13 13
-8 MIN 0.45 0.45 8 10 MAX 0.55 0.55 13 13 UNITS
tCK tCK
ns ns
SYMBOL tIH tIS tRFC
tRP
-75Z MIN MAX 1 1 75 20
MIN 1 1 75 20
-75 MAX
-8 MIN 1.1 1.1 80 20 MAX UNITS ns ns ns ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
SELF REFRESH MODE
T0 CK# CK1
tIS tCH tIH tCL tIS
(( ))
T1
(( )) (( ))
Ta01
Ta1
tCK t IS
(( )) (( ))
Tb0
CKE1
tIS
www..com
tIH AR
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
COMMAND4
NOP
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
NOP
VALID
tIS
tIH
ADDR
VALID
DQS
DQ
DM
tRP2
tXSNR/ tXSRD3
Enter Self Refresh Mode
Exit Self Refresh Mode
DON'T CARE
NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. Device must be in the all banks idle state prior to entering self refresh mode. 3. tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied. 4. AR = AUTO REFRESH command.
TIMING PARAMETERS
-75Z SYMBOL tCH tCL
tCK (2.5) tCK (2) tIH
-75 MIN 0.45 0.45 7.5 10 1 MAX 0.55 0.55 13 13 MIN 0.45 0.45 8 10 1.1
-8 MAX 0.55 0.55 13 13 UNITS tCK tCK ns ns ns SYMBOL tIS
tRP tXSNR tXSRD
-75Z MIN 1 20 75 200 MAX MIN 1 20 75 200
-75 MAX MIN 1.1 20 80 200
-8 MAX UNITS ns ns ns tCK
MIN 0.45 0.45 7.5 7.5 1
MAX 0.55 0.55 13 13
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
62
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
BANK READ - WITHOUT AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8
CK# CK
tIS
tIH
tCK
tCH
tCL
CKE
tIS tIH ACT tIS RA tIH Col n RA NOP6 READ2 NOP6 PRE7 NOP6 NOP6 ACT
COMMAND5
NOP6
www..com
x4: A0-A9, A11, A12 x8: A0-A11 x16: A0-A9 x8: A12 x16: A11, A12
RA tIS tIH
ALL BANKS
RA
A10
RA tIS tIH
3
ONE BANK
RA
BA0, BA1
Bank x tRCD tRAS7 tRC
Bank x
Bank x4
Bank x
CL = 2
tRP
DM
Case 1: tAC(MIN) and tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
DQS
tLZ(MIN)
DQ1
tLZ(MIN)
DO n tAC(MIN) tHZ(MIN)
Case 2: tAC(MAX) and tDQSCK(MAX)
tRPRE
tDQSCK(MAX) tRPST
DQS
tLZ(MAX)
DQ1
tLZ(MAX)
DO n tAC(MAX) tHZ(MAX)
NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
DO n = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The PRECHARGE command can only be applied at T5 if tRAS minimum is met. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
TRANSITIONING DATA DON'T CARE
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
63
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
BANK READ - WITH AUTO PRECHARGE
CK# CK
tIS tIH tCK tCH tCL
T0
T1
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CKE
tIS tIH ACT tIS tIH Col n RA NOP5 READ2,6 NOP5 NOP5 NOP5 NOP5 ACT
COMMAND4
NOP5
x4: A0-A9, A11,A12 www..com
x8: A0-A9, A11 x16: A0-A9 x8: A12 x16: A11, A12
RA
RA 3
RA
A10 IS BA0, BA1
RA
tIS
tIH
RA
IH
Bank x tRCD, tRAP6 tRAS tRC Bank x
Bank x
CL = 2
tRP
DM
Case 1: tAC(MIN) and tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
DQS
tLZ(MIN)
DQ1
tLZ(MIN)
DO n tAC(MIN) tHZ(MIN)
Case 2: tAC(MAX) and tDQSCK(MAX)
tRPRE
tDQSCK(MAX) tRPST
DQS
tLZ(MAX) DO n tLZ(MAX) tAC(MAX) tHZ(MAX)
DQ1
NOTE: 1. 2. 3. 4. 5. 6. 7.
DO n = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Enable auto precharge. ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The READ command can only be applied at T3 if tRAP is satisfied at T3 Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
TRANSITIONING DATA DON'T CARE
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
64
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
BANK WRITE - WITHOUT AUTO PRECHARGE
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5 x4: A0-A9, A11, A12 x8: A0-A9, A11
NOP6
www..com A0-A9 x16:
x8: A12 x16: A11, A12
RA
RA tIS tIH
ALL BANKS
A10
RA tIS tIH
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x tWR
Bank x4
tRP tDQSS(NOM)
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM tDS
DI b
tDH TRANSITIONING DATA DON'T CARE
NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
DI n = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TIMING PARAMETERS
-75Z SYMBOL tCH
tCL tCK (2.5) tCK (2) tDH tDS tDQSH tDQSL tDQSS tDSS
-75 MIN 0.45 0.45 7.5 10 0.5 0.5 0.35 0.35 0.75 0.2 MAX 0.55 0.55 13 13 MIN 0.45 0.45 8 10 0.6 0.6 0.35 0.35 0.75 0.2
-8 MAX 0.55 0.55 12 12 UNITS tCK
tCK
-75Z SYMBOL tDSH tIH
tIS tRAS tRCD tRP tWPRE tWPRES tWPST tWR
-75 MIN 0.2 1 1 40 20 20 0.25 0 0.4 15 MAX MIN 0.2 1.1 1.1 40 20 20 0.25 0 0.4 15
-8 MAX UNITS tCK ns ns ns ns ns
tCK
MIN 0.45 0.45 7.5 7.5 0.5 0.5 0.35 0.35 0.75 0.2
MAX 0.55 0.55 13 13
MIN 0.2 1 1 40 20 20 0.25 0 0.4 15
MAX
ns ns ns ns
tCK tCK tCK tCK
120,000
120,000
120,000
ns 0.6
tCK
1.25
1.25
1.25
0.6
0.6
ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
65
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
BANK WRITE - WITH AUTO PRECHARGE
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP5 WRITE2 NOP5 NOP5 NOP5 NOP5 NOP5
COMMAND4
NOP5
x4: A0-A9, A11 www..com x8: A0-A9 x16: A0-A8 x4: A12 x8: A11, A12 x16: A9, A11, A12 A10
tIS
RA
RA 3 RA tIH Bank x tRCD tRAS tDQSS(NOM) tWR tRP tIS tIH
BA0, BA1
Bank x
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
NOTE: 1. 2. 3. 4. 5. 6. 7.
DI n = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Enable auto precharge. ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA DON'T CARE
TIMING PARAMETERS
-75Z SYMBOL tCH
tCL tCK (2.5) tCK (2) tDH tDS tDQSH tDQSL tDQSS tDSS
-75 MIN 0.45 0.45 7.5 10 0.5 0.5 0.35 0.35 0.75 0.2 MAX 0.55 0.55 13 13 MIN 0.45 0.45 8 10 0.6 0.6 0.35 0.35 0.75 0.2
-8 MAX 0.55 0.55 13 13 UNITS tCK
tCK
-75Z SYMBOL tDSH tIH
tIS tRAS tRCD tRP tWPRE tWPRES tWPST tWR
-75 MIN 0.2 1 1 40 20 20 0.25 0 0.4 15 MAX MIN 0.2 1.1 1.1 40 20 20 0.25 0 0.4 15
-8 MAX UNITS tCK ns ns ns ns ns
tCK
MIN 0.45 0.45 7.5 7.5 0.5 0.5 0.35 0.35 0.75 0.2
MAX 0.55 0.55 13 13
MIN 0.2 1 1 40 20 20 0.25 0 0.4 15
MAX
ns ns ns ns
tCK tCK tCK tCK
120,000
120,000
120,000
ns 0.6
tCK
1.25
1.25
1.25
0.6
0.6
ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
66
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
WRITE - DM OPERATION
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5 x4: A0-A9, A11 x8: A0-A9 www..com x16: A0-A8 x4: A12 x8: A11, A12 x16: A9, A11, A12 A10
NOP6
RA
RA tIS RA tIS tIH Bank x tRCD tRAS tDQSS(NOM) 3
ONE BANK
tIH
ALL BANKS
BA0, BA1
Bank x
Bank x4
tWR tRP
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
DI n = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA DON'T CARE
TIMING PARAMETERS
-75Z SYMBOL tCH
tCL tCK (2.5) tCK (2) tDH tDS tDQSH tDQSL tDQSS tDSS
-75 MIN 0.45 0.45 7.5 10 0.5 0.5 0.35 0.35 0.75 0.2 MAX 0.55 0.55 13 13 MIN 0.45 0.45 8 10 0.6 0.6 0.35 0.35 0.75 0.2
-8 MAX 0.55 0.55 13 13 UNITS tCK
tCK
-75Z SYMBOL tDSH tIH
tIS tRAS tRCD tRP tWPRE tWPRES tWPST tWR
-75 MIN 0.2 1 1 40 20 20 0.25 0 0.4 15 MAX MIN 0.2 1.1 1.1 40 20 20 0.25 0 0.4 15
-8 MAX UNITS tCK ns ns ns ns ns
tCK
MIN 0.45 0.45 7.5 7.5 0.5 0.5 0.35 0.35 0.75 0.2
MAX 0.55 0.55 13 13
MIN 0.2 1 1 40 20 20 0.25 0 0.4 15
MAX
ns ns ns ns
tCK tCK tCK tCK
120,000
120,000
120,000
ns 0.6
tCK
1.25
1.25
1.25
0.6
0.6
ns
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01
67
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16 DDR SDRAM
(TG) OPTION 66-PIN PLASTIC TSOP (400 MIL)
SEE DETAIL A 0.71 0.65 TYP 0.32 .075 TYP 0.10 (2X)
22.22 0.08
www..com
11.76 0.10 10.16 0.08
PIN #1 ID
+0.03 0.15 -0.02
GAGE PLANE
0.25
0.10 0.10 1.20 MAX
+0.10 -0.05 0.80 TYP 0.50 0.10 DETAIL A
NOTE:
MAX or typical here noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 1. All dimensions in millimeters
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
512Mb: x4, x8, x16 DDR SDRAM 512Mx4x8x16DDR_B.p65 - Rev. B; Pub 4/01 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
68

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